To meet the size and cost challenges of large embedded memory modules, a paradigm shift is needed. A nonvolatile memory architecture called the Micro-flash1 process, compatible with standard CMOS (complementary metal oxide semiconductor) processes, is vying to be part of this shift is. The Micro-flash module supports a high degree of miniaturization owing to its inherently small cell size and this allows for efficient embedding of flash and EEPROM (electrically erasable programmable read-only memory) modules.

The work presented here, most done through refining the programming and erase functionality on a dual-voltage device, began with a feasibility study in 1997, continued with process development work in 1998, and commercialization of the process in 1999. In this article, we present the theory, structure and principle of operation for the Micro-flash process along with comparison data and validation results.

Principles of operation

Embedding large memory arrays has usually been a complex process involving many additional layers, using processes not compatible with each other [1,2]. The Micro-flash process uses NROM (non-volatile read only memory) technology that was developed by Dr. Boaz Eitan [3]. The Micro-flash cell is an n-channel MOSFET (metal oxide semiconductor field-effect transistor) device in which the gate dielectric is replaced with a trapping material (nitride) sandwiched between two silicon dioxide layers (Oxide-Nitride-Oxide = ONO) [3-7]. The top and bottom oxides are thicker than 50 angstroms to avoid any direct tunneling. The charge is stored in the nitride next to the N+ junctions. The cell stores two physically separated bits with a unique method to sense the trapped charge.

The localized trapping concept and the unique reading scheme are the keys to the Micro-flash cell operation. The trapping mechanism builds-up a sufficient potential to enable it to be read externally. Moreover, each edge of the ONO layer can store charge independently, thereby enabling the writing of two bits in each cell. Thus the technological foundation of the Micro-flash cell allows it to be four to six times smaller than equivalent flash technologies. A standard CMOS transistor is open to current flow between source and drain because the gate potential lowers the energy gap between source and channel. In a Micro-flash device a relatively small charge at the source prevents current flow, while a charge of the same value at the drain allows current flow. Programming is performed by channel hot electron (CHE) injection. Erasing is accomplished using tunnel-enhanced hot hole injection.

Programming of bit 1 is performed by setting VBL1 to zero volts and VBL2 to between four and five volts, in a stepped algorithm, while maintaining VWL at 9 volts (see Figure 1). Electrons are injected and trapped next to junction BL2. Reading bit 1 is accomplished by applying 1.6 volts to BL1, 0 volts to BL2, and approximately 3 volts to VWL. To maximize the sensitivity of the read operation, the stored charge is sensed next to the source terminal. A low voltage applied to BL1 further enhances the read sensitivity by minimizing the potential drop across the trapped charge. The second bit is programmed and read by reversing the terminals in both operations. The narrow, trapped-charge region (approximately 100 to 150 angstroms wide) is the reason one bit doesn't affect the information contained in the other bit (cross-talk).

The narrow region permits "read through" of the trapped charge region at each edge, indicating a true two-bit capability.

Figure 1 - Bit separator

In the first cycle only Bit 1 is programmed and Bit 2 remains erased. In the 2nd cycle the reverse is true.

Bit erasing a programmed bit is accomplished by applying a high voltage to the bit line, thereby creating band-to-band tunneling and a lateral field effect. This causes hole injection through the bottom oxide layer of the ONO stack. The injection probability is strongly dependent on the vertical field. The bit line voltage affects both the lateral and vertical fields, hence erasing is more sensitive to the VBL value. The fact that one bit doesn't affect the other results from the electrical insulation of the ONO layer. We found that the two bits above the source and drain remained isolated even when the distance between them was reduced to 0.1 micron. This distance is equivalent to that found in a 0.13-micron process. We think that this finding establishes the portability of the Micro-flash cell to deep-submicron manufacturing processes.

Micro-flash architecture and manufacturing

A Micro-flash memory array is formed by placing Micro-flash cells in a virtual ground architecture that assures the symmetry between the source and the drain. The symmetry provides the mechanism to address each of the two bits per cell. The array consists of bit lines and word lines in a cross-wise pattern. The bit lines are formed of buried N+ implants. Word lines are a composite layer of polycide on polysilicon. The ONO layer covers the space between the N+ bit lines. Thin oxidation of the bit lines reduces capacitance between the bit lines and the word lines. The lithography and minimum effective channel length (Leff) limit cell size. In floating gate technology, drain coupling may require enlarging the cell size to accommodate considerations such as current leakage and slower programming times. In the Micro-flash cell, however, coupling is equal tone; hence increase in size isn't required.

The Micro-flash process requires only five additional masking steps over the standard CMOS process. Three masks generate the array and the other two form the high-voltage transistors. This simplicity is a major advantage over conventional Flash technology.

The Micro-flash cell is formed after the well and isolation modules with minimal impact on the thermal cycles (see Figure 2). Adding Micro-flash modules doesn't change the characteristics of the standard CMOS process.

The simplicity of the Micro-flash manufacturing process comes from requiring only three additional masks to form the array, and a single layer of polysilicon-thus saving the cost and complexity of multiple depositions and etching steps. The single layer eliminates the potential defects associated with multiple layers, thus contributing to higher yield. Fewer masks result in an inherently lower defect density.

Figure 2 - Micro-flash cell

A scannign electron microscope (SEM) cross-section of a Micro-flash cell.

The validity of the above points was demonstrated in actual testing of the two-Mbit development product. We found that the yield loss due to defects was only 5 percent at the start of production without any defect-reduction programs in place and no redundancy implemented.

Validation data

The high reliability of the Micro-flash cell stems from the localized trapping mechanism. Since charge transfer occurs between every trap and the silicon substrate or polysilicon layer in the Micro-flash cell, local dielectric defect cannot cause the loss of the entire charge. Also, localized erasing eliminates the problem of over-erase. We measured retention in Micro-flash devices in various baking and high temperature storage life (HTSL) tests and found that the retention in Micro-flash devices proved equivalent to floating gate device performance. We attributed this capability to the relatively thick bottom and top oxides and the nitride stabilization process.

We also performed extensive process optimization and specialized program-erase algorithm development to achieve the best overlap between hole and electron distributions in the nitride during injections. This effort extended the endurance of Micro-flash modules to full flash performance. Cycling tests demonstrated the capability of the technology to support 100,000 cycles and beyond (see Figure 3). Micro-flash modules and single cells showed similar results. In all of these tests there was no erratic behavior, faster degradation, or any other Vt distribution related issues, as sometimes encountered in floating gate devices.

Figure 3 - Cycling results of the 2mb product

Cycling data shows efficient erase through 100,000 cycles.

Devices benefiting from the Micro-flash process include microprocessors, DSP engines, micro-controllers, or any other component containing high-flash density with RF, analog, logic, or DRAM circuitry.

The technology we've described has been implemented in a family of stand-alone and embedded devices in 0.5-micron technology. These devices used dual-voltage for applications that need only a limited number of program-erase cycles. Currently, we're developing full- flash capability in a single-voltage device using 0.5-micron geometry. Implementation of the technology in 0.18-micron line width is planned in the near future.

Embedded together, the EEPROM array supports direct access at the byte level while the flash module provides area-efficient storage for operating code and large quantities of data. Table 1 compares typical areas of memory modules used in floating gate and Micro-flash processes. As evident from these data, the size advantage of this technology is significant even at low densities such as 0.5 MB.

We believe that all floating-gate devices, EPROM, EEPROM, and flash can be replaced with the applicable Micro-flash version. The benefits of Micro-flash over floating gate devices are its high density (smallest area per bit) and simple CMOS process, which translate to significantly lower device cost. As the industry moves forward, the Micro-flash process is expected to become the technology of choice for large embedded-memory, as well as stand-alone memory applications.

Ilan Bloom is the device group manager at Saifun Semiconductor Ltd (Israel). Prior to Saifun, Blum was a member of the Academic Staff in the Technion--Israel Institue of Technology.